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RFD16N05L, RFD16N05LSM
Data Sheet April 1999 File Number
2269.2
16A, 50V, 0.047 Ohm, Logic Level, N-Channel Power MOSFETs
These are N-Channel logic level power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA09871.
Features
* 16A, 50V * rDS(ON) = 0.047 * UIS SOA Rating Curve (Single Pulse) * Design Optimized for 5V Gate Drives * Can be Driven Directly from CMOS, NMOS, TTL Circuits * Compatible with Automotive Drive Requirements * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Majority Carrier Device * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFD16N05L RFD16N05LSM PACKAGE TO-251AA TO-252AA BRAND RFD16N05L RFD16N05LSM
Symbol
D
NOTE: When ordering, include the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RFD16N05LSM9A
G
S
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE
JEDEC TO-252AA
DRAIN (FLANGE)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFD16N05L, RFD16N05LSM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFD16N05L, RFD16N05LSM 50 50 16 45 10 60 0.48 -55 to 150 300 260 UNITS V V A A V W W/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250mA, VGS = 0V, Figure 10 VGS = VDS, ID = 250mA, Figure 9 VDS = 40V, VGS = 0V TC = 150oC VGS = 10V, VDS = 0V ID = 16A, VGS = 5V ID = 16A, VGS = 4V MIN 50 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 40V, ID = 16A, RL = 2.5 Figures 17, 18 TYP 14 30 42 14 MAX 2 1 50 100 0.047 0.056 60 100 80 45 3 2.083 100 UNITS V V A A nA ns ns ns ns ns ns nC nC nC
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2)
IGSS rDS(ON)
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(5) Qg(TH) RJC RJA
VDD = 25V, ID = 8A, VGS = 5V, RGS = 12.5 Figures 15, 16
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. SYMBOL VSD trr ISD = 16A ISD = 16A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns
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RFD16N05L, RFD16N05LSM Typical Performance Curves Unless Otherwise Specified
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 150 15 0.8 20
0.6 0.4
10
5
0.2 0 125 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
102
IAS, AVALANCHE CURRENT (A)
TC = 25oC TJ = MAX RATED ID MAX CONTINUOUS
102 Idm STARTING TJ = 25oC STARTING TJ = 150oC
ID, DRAIN CURRENT (A)
10 OPERATION IN THIS AREA LIMITED BY rDS(ON) 1 DC
10
If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) 1 0.01 If R 0 tAV = (L/R)ln[(IAS*R)/(1.3 RATED BVDSS - VDD) +1] 0.10 1 tAV, TIME IN AVALANCHE (ms) 10
0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
102
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA (SINGLE PULSE UIS SOA)
IDS(ON), DRAIN TO SOURCE ON CURRENT (A)
45 IDS, DRAIN TO SOURCE CURRENT (A) VGS = 10V VGS = 4V VGS = 5V 30
TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX.
45 VDS = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 30
VGS = 3V 15
15
VGS = 2V 0 0 6.0 1.5 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 7.5
0
0
1.5 3.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V)
6.0
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
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RFD16N05L, RFD16N05LSM Typical Performance Curves Unless Otherwise Specified (Continued)
1.4 2.5 VDS = 15V NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 16V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. ID = 16A 2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX.
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 4
1.5
1.0
0.5
5 6 VGS, GATE TO SOURCE VOLTAGE (V)
7
0 -50
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.4 1.3 NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.1 1.0 0.9 0.8 0.7
NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
ID = 250A VGS = VDS
1.4 ID = 250A 1.2
1.0
0.8
0.6
0.6 -50
0
50
100
150
200
0 -50
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED GATE THRESHOLD vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
1600 C, CAPACITANCE (pF) CISS CISS = CGS + CGD CRSS = CGD COSS CDS + CGD COSS CRSS 0 0 5 10 15 20 25
37.5
8
1200
6
25
800
GATE SOURCE VOLTAGE
4
12.5 2 DRAIN SOURCE VOLTAGE 0 I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 -----------------------I G ( ACT ) 0
400
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
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VGS , GATE TO SOURCE VOLTAGE (V)
VGS = 0V f = 1MHz
VDS , DRAIN TO SOURCE VOLTAGE (V)
2000
50
10 RL = 3.125, VGS = 5V IG(REF) = 0.60mA PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS V = 0.75 BV VDD = BVDSS VDD = 0.50 BVDSS VDD = BVDSS DD DSS VDD = 0.25 BVDSS
RFD16N05L, RFD16N05LSM Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) tr RL VDS
+
tOFF td(OFF) tf 90%
90%
RG DUT
-
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS
12V BATTERY
0.2F
50k 0.3F
G
DUT 0
IG(REF) 0 IG CURRENT SAMPLING RESISTOR
S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORMS
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RFD16N05L, RFD16N05LSM Spice Model
(RFD16N05L)
.SUBCKT RFD16N05L 2 1 3; rev 04/08/92 *Nominal Temperature = 25oC .MODEL MOSMOD NMOS (VTO=2.054 KP=24.73 IS=1e-30 N=10 TOX=1 L=1u W=1u) Vto 21 6 0.448 Rsource 8 7 RDSMOD 0.614E-3 Rdrain 5 16 RDSMOD 27.38E-3 .MODEL RDSMOD RES (TC1=3.66E-3 TC2=1.46E-5) .MODEL RVTOMOD RES (TC1=-1.81E3 TC2=1.41E-6) Ebreak 11 7 17 18 70.9 .MODEL RBKMOD RES (TC1=1.01E-3 TC2=5.21E-8) .MODEL DBKMOD D (RS=8.82E-2 TRS1=-2.01E-3 TRS2=7.32E-10) .MODEL DBDMOD D (IS=1.34E-13 RS=1.21E-2 TRS1=1.64E-3 TRS2=2.59E-6 +CJO=1.13E-9 Cin 6 8 1.21E-9 Ca 12 8 3.33E-9 .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.25 VOFF=-2.25) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.25 VOFF=-4.25) .MODEL DPLCAPMOD D (CJO=5.22E-10 IS=1e-30 N=10) Cb 15 14 3.11E-9 .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.65 VOFF=4.35) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.35 VOFF=-0.65) Rgate 9 20 2.98 Lgate 1 9 1.38E-9 Ldrain 2 5 1.0E-12 Lsource 3 7 1.0E-9 Dbody 7 5 DBDMOD Dbreak 5 11 DBKMOD Dplcap 10 5 DPLCAPMOD Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evto 20 6 18 8 1 It 8 17 1 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 Rbreak 17 18 RBKMOD 1 Rin 6 8 1e9 Rvto 18 19 RVTOMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 8 19 DC 1 .ENDS
TT=4.14E-8)
x
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